1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more particularly, it relates to a structure for implementing a high-speed operation and low power consumption in a semiconductor integrated circuit device including MOS transistors (insulated gate field effect transistors) as its components.
2. Description of the Background Art
Following densification of a semiconductor integrated circuit device such as logic and a memory circuit, elements are refined and it is necessary to reduce the power supply voltage in order to insure the breakdown voltage of these elements. If the semiconductor integrated circuit device is composed of MOS transistors, however, the driving speed for signal lines varies with the gate potentials of these MOS transistors (a so-called square characteristics of a drain current), and hence the operating speed of the circuit is reduced. In order to avoid such reduction of the operating speed, the absolute value of the threshold voltage Vth of each MOS transistor must be reduced. A value Vgs-Vth is increased to increase the drain current, where Vgs represents the gate-to-source voltage. Due to the reduction of the absolute value of the threshold voltage Vth, the MOS. transistor enters a conducting state at a fast timing for supplying the drain current, and high-speed charging/discharging of the signal line is implemented.
In general, the relation between the power supply voltage Vcc and the threshold voltage Vth with priority to the operating speed is expressed as follows, as shown in Advanced Electronics Series I-9, "VLSI Memory" by Itoh, Baifukan Shuppan, published on Nov. 5, 1994, p. 352, for example: EQU Vth=.alpha..multidot.Vcc
where .alpha. represents a constant which takes a value of 0.1 to 0.2. Assuming that the power supply voltage Vcc is 1 V, for example, the threshold voltage Vth is 0.1 to 0.2 V.
With priority to power consumption in a standby state, on the other hand, a subthreshold current must be taken into consideration. This subthreshold current is defined by a gate-to-source voltage in such a state that a constant drain current I0 starts to flow through a MOS transistor having a certain channel width (W0). This subthreshold current flows even if the gate-to-source voltage Vgs is 0 V. According to Kuroda et al., the subthreshold current as well as standby power are increased when the threshold voltage is reduced to no more than about 0.4 V (refer to Nikkei Microdevices, March 1995, p. 58).
FIG. 27 schematically illustrates changes of threshold voltages Vth of n-channel MOS transistors with respect to a potential difference VBS between a back gate (substrate regions) and a source. Referring to FIG. 27, curves T1 and T2 show threshold voltages Vth of n-channel MOS transistors, which are at the levels of 0.1 V and 0.28 V when the back gate-to-source potential differences VBS are 0 V respectively. Referring to FIG. 27, the axis of ordinates measures the threshold voltages VTh, and the axis of abscissas measures the back gate-to-source potential differences VBS. Each of these curves T1 and T2 is obtained in accordance with the following equation (1), on the assumption that a substrate effect constant K described later is 0.4: EQU Vth=VTH0+.vertline.K.vertline.(2.multidot..PHI.F-VBS.vertline.).sup.1/2 -(.vertline.2.multidot..phi.F.vertline.).sup.1/2 ! (1)
where VBS represents the back gate potential (back gate-to-source voltage) with reference to the source potential, K represents the substrate effect constant, .PHI.F represents the substrate surface potential, and VTH0 represents the threshold voltage obtained when the back gate-to-source potential difference VBS is 0 V.
As clearly understood from the characteristic curve T1 shown in FIG. 27, the threshold voltage Vth is increased when the back gate potential with reference to the source potential, i.e., the back gate-to-source voltage VBS is increased in the negative direction in the n-channel MOS transistor. For example, it is assumed that an n-channel MOS transistor having a threshold voltage Vth0 when the back gate-to-source voltage VBS is 0 V is formed by controlling the amount of implanted ions into the gate region of the n-channel MOS transistor (characteristic curve T1). In order to increase the threshold voltage Vth of this n-channel MOS transistor to 0.4 V, the back gate-to-source voltage VBS must be reduced to -1.71 V, from this characteristic curve T1. In other words, the threshold voltage of the n-channel MOS transistor can be changed by controlling the back gate-to-source voltage VBS.
FIG. 28 schematically illustrates the relations between gate potentials Vgs of n-channel MOS transistors with reference to source potentials and drain currents Ids. Referring to FIG. 27, the axis of abscissas measures the gate potentials (hereinafter referred to as gate voltages) with reference to the source potentials, and the axis of ordinates measures the drain currents in logarithmic scale. Characteristic curves TS1 and TS2 show drain currents flowing when the back gate-to-source voltages VBS are 0 V and -1.71 V respectively. Referring to the characteristic curves TS1 and TS2 shown in FIG. 28, substantially linear regions are called subthreshold regions.
Comparing the characteristic curves TS1 and TS2 with each other, it is clearly understood that the subthreshold current (drain current) flowing when the back gate-to-source voltage VBS is 0 V is larger than that flowing when the back gate-to-source voltage VBS is -1.71 V. When the back gate-to-source voltage VBS is 0 V, even when the gate voltage Vgs is low, a relatively large current flows due to reduction of the threshold voltage by 0.3 V. If an n-channel MOS transistor with the characteristic curves TS1 and TS2 in an active period, i.e., in a circuit operation and in a standby cycle respectively is employed, implemented is an n-channel MOS transistor operating at a high speed with a subthreshold current sufficiently suppressed in a standby state.
FIG. 29 illustrates an exemplary structure of a conventional back gate voltage switching circuit for an n-channel MOS transistor. Referring to FIG. 29, the back gate voltage switching circuit includes an invertor 5 operating with a power supply voltage Vcc on a power supply line 1 and a ground voltage Vss on a ground line 2 as operating power supply voltages, for inverting an activation signal SNB supplied on an input signal line 3 and outputting the inverted signal onto an output signal line 4, a level conversion circuit 10 converting the voltage level of the signal supplied from the invertor 5 onto the output signal line 4 to the level of the power supply voltage Vcc or a negative voltage VNBL, and a back gate driving circuit 15 outputting either the ground voltage Vss or the negative voltage VNBL in accordance with an output signal of the level conversion circuit 10.
A back gate voltage VNB from the back gate driving circuit 15 is supplied to a back gate (substrate region) of an n-channel MOS transistor Q included in an internal circuit 18 through an output signal line 16. The activation signal SNB indicates activation/inactivation of the internal circuit 18, and the internal circuit 18 operates when the activation signal SNB is at a high level, while remaining in an inactive state and holding a standby state when the signal SNB is at a low level.
The level conversion circuit 10 includes a p-channel MOS transistor 10a which conducts in response to the signal on the output signal line 4 for transmitting the power supply voltage Vcc on the power supply line 1 to an internal node 11a, a p-channel MOS transistor 10b which conducts in response to the activation signal SNB for transmitting the power supply voltage Vcc on the power supply line 1 to an internal node 11b, an n-channel MOS transistor 10c which conducts in response to the signal potential on the internal node 11b for transmitting a low-level back gate voltage VNBL on a back gate voltage supply line 14 to the internal node 11a, and an n-channel MOS transistor 10d which conducts in response to the signal potential on the internal node 11a for transmitting the low-level back gate voltage VNBL to the internal node 11b.
The back gate driving circuit 15 includes an n-channel MOS transistor 15a which conducts in response to the signal potential on the internal node 11a for transmitting the voltage Vss on a high-level back gate voltage supply line 17 to the output signal line 16, and an n-channel MOS transistor 15b which conducts in response to the signal potential on the internal node 11b for transmitting the low-level back gate voltage VNBL to the output signal line 16. The high-level back gate voltage supply line 17, which transmits a high-level back gate voltage, i.e., the ground voltage Vss, is equivalent to a ground line. The ground voltage Vss is 0 V, and the low-level back gate voltage VNBL is -1.71 V, for example. The term"back gate voltage" indicates a voltage measured with reference to the ground voltage. The operation of the back gate voltage switching circuit shown in FIG. 29 is now briefly described.
When the internal circuit 18 is in an inactive and standby state, the activation signal SNB is at a low level, and the signal outputted from the invertor 5 to the output signal line 4 goes high to the level of the power supply voltage Vcc. In this state, the p-channel MOS transistors 10a and 10b enter non-conducting and conducting states respectively, and the internal node 11b is charged by the p-channel MOS transistor 10b. In accordance with the potential increase of the internal node 11b, the n-channel MOS transistor 10c conducts to reduce the potential of the internal node 11a to the level of the negative back gate voltage VNBL. Following the potential reduction of the internal node 11a, the n-channel MOS transistor 10d enters a non-conducting state. Thus, the internal node 11b is charged to the level of the power supply voltage Vcc by the p-channel MOS transistor 10b, while the internal node 11a is discharged to the level of the negative back gate voltage VNBL.
The level of the negative back gate voltage VNBL is lower than the ground voltage Vss, and the n-channel MOS transistor 15a enters a non-conducting state, while the n-channel MOS transistor 15b receiving the power supply voltage Vcc at its gate conducts to transmit the low-level negative back gate voltage VNBL to the back gate of the n-channel MOS transistor Q included in the internal circuit 18 as the back gate voltage VNB. In the standby state of the internal circuit 18, therefore, the threshold voltage of the n-channel MOS transistor Q is increased to suppress a subthreshold current.
When the internal circuit 18 operates in an active cycle, on the other hand, the activation signal SNB goes high and the signal outputted from the invertor 5 onto the output signal line 4 is brought to the level of the ground voltage Vss. Thus, the p-channel MOS transistors 10a and 10b enter conducting and non-conducting states respectively. In this state, the n-channel MOS transistors 10c and 10d enter non-conducting and conducting states respectively contrarily to the aforementioned standby cycle, and the voltages of the internal nodes 11a and 11b are brought to the levels of the power supply voltage Vcc and the negative back gate voltage VNBL respectively. Therefore, the n-channel MOS transistors 15b and 15a enter non-conducting and conducting states, and the ground voltage Vss is supplied as the back gate voltage VNB. Thus, the threshold voltage of the n-channel MOS transistor Q of the internal circuit 18 is reduced so that the n-channel MOS transistor Q performs a switching operation at a high speed.
Also as to a back gate voltage for a p-channel MOS transistor included in the internal circuit 18, a similar effect can be attained by replacing the back gate voltage VNB for the n-channel MOS transistor Q with a voltage at the level of the power supply voltage Vcc or a higher level. As to the relation between the threshold voltage and the back gate-to-source voltage of the p-channel MOS transistor, the sign of the back gate-to-source voltage VBS may be inverted in each characteristic curve shown in FIG. 27, while subthreshold current characteristics of the p-channel MOS transistor can be obtained by inverting the sign of each gate voltage vgs shown in FIG. 28.
As hereinabove described, a high-speed operation in an active cycle and low power consumption in a standby cycle can be implemented by switching the back gate voltage for each MOS transistor depending on the operating cycle. However, the level conversion circuit 10, which is employed for switching the back gate voltage, changes the level of the signal changing between the power supply voltage Vcc and the ground voltage Vss to the level of the power supply voltage Vcc or the negative back gate voltage VNBL. In this case, the power supply voltage Vcc is applied to the gate of the n-channel MOS transistor 15b included in the back gate driving circuit 15 in the standby cycle of the internal circuit 18 with the activation signal SNB at a low level. Assuming that the power supply voltage is 1.0 V, the gate-to-source voltage of the n-channel MOS transistor 15n is Vcc-VNBL=1.0-(-1.71)=2.71 V, and it follows that a large voltage of 2.71 times the gate-to-source voltage (1.0 V) of an n-channel MOS transistor included in the invertor 5 is applied, for example.
Also in the level conversion circuit 10, the voltage of 2.71 V is applied between the gate and the drain of each of the non-conductive p-channel MOS transistors 10a and 10b while a voltage of 2.71 V is similarly applied between the gate and the source of each of conductive the n-channel MOS transistors 10c and 10d. Consequently, large electric fields are applied across respective insulating films of gate electrode parts of these MOS transistors, to disadvantageously reduce the reliability of the insulating films.
FIG. 30 illustrates another exemplary conventional back gate voltage switching circuit, which is shown in Nikkei Microdevices, March 1995, p. 59, for example. The back gate voltage switching circuit shown in FIG. 30 applies a back gate voltage VNB to a back gate of an n-channel MOS transistor.
Referring to FIG. 30, the back gate voltage switching circuit includes a p-channel MOS transistor 22 which is connected between a power supply line 20 transmitting a power supply voltage Vcc and an internal node 21 for receiving an activation signal /CE at its gate, a p-channel MOS transistor 24 which is connected between the internal node 21 and an internal node 23 and has a gate connected to a ground line 25 transmitting a ground voltage Vss, diodes 26a and 26b serially connected between the internal node 23 and an internal node 24, and an n-channel MOS transistor 28 which is connected between the internal node 24 and a back gate voltage transmission line 27 transmitting a low-level back gate voltage VNBL and has a gate connected to the ground line 25. The back gates of the MOS transistors 22 and 24 are connected to the power supply line 20, while that of the MOS transistor 28 is connected to the low-level back gate voltage transmission line 27.
The back gate voltage switching circuit further includes a p-channel MOS transistor 29a and an n-channel MOS transistor 29b forming an invertor which operates with the ground voltage Vss on the ground line 25 and the low-level back gate voltage VNBL on the low-level back gate voltage transmission line 27 as operating power supply voltages for inverting a signal on the internal node 24, and a p-channel MOS transistor 31a and an n-channel MOS transistor 31b forming an invertor for inverting an output signal transmitted from the invertor (the MOS transistors 29a and 29b) onto an internal node 30 and outputting a back gate voltage VNB onto a signal line 32. Back gates of the p-channel MOS transistors 29a and 31a are connected to the power supply line 20, and those of the n-channel MOS transistors 29b and 31b are connected to the low-level back gate voltage transmission line 27. The operation is now briefly described.
The MOS transistors 24 and 28 receive the ground voltage Vss at the gates thereof, and operate as resistive elements. The power supply voltage Vcc is equalized in absolute value with the low-level back gate voltage VNBL. The power supply voltage Vcc is 2.0 V, for example, and the low-level back gate voltage VNBL is -2.0 V.
When the activation signal /CE is at a high level and an internal circuit is an inactive and standby state, the MOS transistor 22 is in a non-conducting state and the node 24 is held at the level of the low-level back gate voltage VNBL by the MOS transistor 28. In response to this, the MOS transistors 29a and 29b enter conducting and non-conducting states respectively, and the voltage on the internal node 30 is brought to the level of the ground potential Vss. In response to the ground voltage Vss on the internal node 30, the MOS transistors 31a and 31b enter non-conducting and conducting states respectively, and the back gate voltage VNB from the signal line 32 is brought to the level of the low-level back gate voltage VNBL. Thus, the back gate voltage of the n-channel MOS transistor included in the internal circuit is brought to the level of the low-level back gate voltage VNBL, and its threshold voltage is increased.
When the activation signal /CE is at a low level and the internal circuit operates in an active cycle, on the other hand, the MOS transistor 22 conducts to transmit the power supply voltage Vcc to the node 23. Due to level shifting by the diodes 26a and 26b, the voltage of the node 24 exceeds the level of the ground voltage Vss, the MOS transistors 29a and 29b enter non-conducting and conducting states respectively, and the voltage on the internal node 30 is brought to the level of the low-level back gate voltage VNBL. In response to this, the MOS transistors 31b and 31a enter non-conducting and conducting states respectively, and the back gate voltage VNB on the signal line 32 is brought to the level of the ground voltage Vss. Thus, the n-channel MOS transistor of the internal circuit has the threshold voltage decreased, to attain a high-speed operation.
In the back gate voltage switching circuit shown in FIG. 30, a level shift circuit employing the diodes 26a and 26b prevents application of a voltage of the sum of the power supply voltage Vcc and the absolute value of the low-level back gate voltage VNBL between the gate and the source of each MOS transistor, thereby ensuring the reliability of the element.
In the structure shown in FIG. 30, however, a current path from the power supply line 20 to the low-level back gate voltage transmission line 27 is formed when the activation signal /CE goes low, and a current flows from the power supply line 20 to the line 27 in an active cycle. Thus, the level of the low-level back gate voltage VNBL is increased, and in order to absorb this voltage increase, the low-level back gate voltage VNBL is required to be supplied from the exterior. In case of generating the low-level back gate voltage VNBL on chip, it is necessary to absorb the current flowing through the current path formed by the MOS transistors 22 and 24, the diodes 26a and 26b and the transistor 28 and hold the back gate voltage VNBL at a constant voltage level. Thus, it is necessary to employ a back gate voltage generation circuit having high current drivability, with a large occupying area. When such a back gate voltage generation circuit having high drivability is employed, current consumption of the circuit is increased and an unnecessary current is consumed. Thus, the structure of the back gate voltage switching circuit shown in FIG. 30 is unsuitable for employment in an on-chip back gate voltage generation circuit.
FIG. 31 illustrates the structure of still another exemplary back gate voltage switching circuit, which is described in Japanese Patent Laying-Open No. 6-21443 (1994), for example. The back gate voltage switching circuit shown in FIG. 31 includes a switching circuit 35 selecting one of a positive voltage Vb and a ground voltage Vss in accordance with a standby detection signal SD. The voltage selected by the switching circuit 35 is supplied to a back gate of an n-channel MOS transistor 40a which is a component included in an internal circuit 40.
When the standby detection signal SD indicates that the internal circuit 40 is in the standby state, the switching circuit 35 selects the ground voltage Vss and supplies the same to the back gate of the MOS transistor 40a. When the standby detection signal SD indicates an active cycle of the internal circuit 40, on the other hand, the switching circuit 35 selects the positive voltage Vb and supplies the same to the back gate of the MOS transistor 40a.
In the structure shown in FIG. 31, a back gate voltage is formed by the positive back gate voltage Vb or the ground voltage Vss, and no large voltage is generated in back gate switching (the difference between a power supply voltage Vcc and the back gate voltage Vb is smaller than the power supply voltage Vcc). When a threshold voltage Vth of the MOS transistor 40a is changed by switching the back gate voltage between the positive voltage Vb and the ground voltage Vss through the switching circuit 35 shown in FIG. 31, however, the following problems arise:
Consider that the threshold voltage Vth of the MOS transistor 40a is brought to 0.1 V when a back gate-to-source voltage VBS is at the level of the positive voltage Vb and brought to 0.4 V when the back gate-to-source voltage VBS is 0 V. As shown in FIG. 32, the value of the voltage Vb, which cannot exceed a built-in voltage (diffusion potential) of 1.0 V of a P-N junction, is smaller than 1.0 V. In order to satisfy the threshold voltage conditions required in case of employing this voltage Vb, therefore, it is necessary to implement a characteristic curve T3 having a considerably steep gradient. In this case, a substrate effect constant K must be increased, from the previous equation (1). This substrate effect constant K is generally expressed as follows: ##EQU1## where tox represents the thickness of a gate insulating film, .epsilon.ox represents the dielectric constant of the gate insulating film, .epsilon.si represents the dielectric constant of a silicon film, NB represents the impurity concentration of a substrate, and q represents a unit electric charge quantity. In order to increase the substrate effect constant K, therefore, the impurity concentration of a substrate region must be increased. Thus, a depletion layer is narrowed, a gate capacitance is increased in response to this, and high-speed operation can not be performed. When the width of the depletion layer is reduced, electric field intensity across this P-N junction, which is inversely proportional to the depletion layer width, is increased, the break-down voltage of the P-N junction is reduced, and the reliability of the element is deteriorated.
When the impurity concentration of the substrate region is increased, further, a diffusion current is generated in proportion to the difference between the impurity concentration of the substrate region and that in a source/drain impurity region of the MOS transistor, and a reverse current (current flowing when a reverse-biased voltage is applied across the P-N junction) is increased in response, to disadvantageously destroy data stored in a memory cell when this MOS transistor is a memory cell transistor, for example. In addition, a leakage current is increased by this reverse current, to disadvantageously increase current consumption.
In case of setting the threshold voltage Vth in accordance with the characteristic curve T3 as shown in FIG. 32, the threshold voltage Vth is remarkably changed by a slight change of the back gate-to-source voltage VBS, and it is difficult to precisely establish a prescribed threshold voltage. When the back gate-to-source voltage VBS is applied in accordance with the characteristic curve T1, on the other hand, the characteristic curve T1 is so gradually changed that the threshold voltage Vth is changed at a rate sufficiently smaller than that of the characteristic curve T3 even if the back gate-to-source voltage VBS is slightly changed. Thus, a prescribed threshold voltage Vth can be stably established.